Title:
HYSTERESIS COMPARATOR
Document Type and Number:
Japanese Patent JP3183187
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent the genereation of abnormal output oscillation by preparing plural reference voltage levels, switching reference voltage to be used for comparison and generating hysteresis before an input signal reaches the reference voltage due to its rise or drop and a compared result is inverted.
SOLUTION: In the OFF state of all transistors(TRs) Q9, Q12, Q15, 1st reference voltage VREF0 obtained by dividing power supply voltage VCC by resistors R1, R2, is applied to a TR Q2. When the TR Q15 is turend on, a resistor R10 is connected in parallel with the resistor R2 and the reference voltage VREF0 is dropped to 2nd reference voltage VREF1 (VREF1<VREF0) and hysteresis is generated. Thereby voltage V1 is quickly dropped, the TR Qq, is turned on and an output signal VOUT is inverted from a low level to a high level. Finally the TR Q12 is turned on, resistors R10, R3 are connected in parallel with the resistor R2 and the reference voltage VREF1 is dropped to 3rd reference voltage VREF2 (VREF2 < VREF1).
Inventors:
Hikaru Watanabe
Application Number:
JP23318696A
Publication Date:
July 03, 2001
Filing Date:
September 03, 1996
Export Citation:
Assignee:
TOYOTA JIDOSHA KABUSHIKI KAISHA
International Classes:
H03K3/2893; H03K3/0233; H03K5/08; (IPC1-7): H03K5/08; H03K3/0233
Attorney, Agent or Firm:
Tadahiko Ito