To realize high reliability for an MRAM by providing it with a function for adjusting pulse width for a write current value depending on the temperature and preventing it from a write error.
The device is configured with a memory cell array 12 on which magnetoresistance effect elements, memory elements for the MRAM, are arranged in a two dimensional plane, a first wiring WL for writing data and a second wiring BL for writing data on the magnetoresistance effect element selectively by a current field generated by the current in rows and the current field generated by the current in columns, and a control circuit 22 for controlling temperature dependence on write pulse current for at least one of the write pulse current flowing through the first wiring for writing and the write pulse current flowing through the second wiring for writing.
SHIMIZU ARITAKE
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto
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