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Title:
MAIN MEMORY CONTROL METHOD
Document Type and Number:
Japanese Patent JP06324943
Kind Code:
A
Abstract:

PURPOSE: To provide a main memory control method and a memory system using the same for accelerating the control of cache hit access at a main memory controller provided with a cache memory connected to the same bus as a main memory which is equipped with an ECC function, and having the ECC function similar to that of the main memory.

CONSTITUTION: Concerning the memory system composed of a main memory controller 2 for controlling the main memory and the cache memory, in the case of cache hit when executing read access to a main memory 4 or a cache memory 3, read data are sent to a CPU 1, at the same time, the ECC code check of read data is parallelly performed inside the main memory controller 2, when the result of the ECC code check is any correctable data error, data for which the error is detected are corrected at the time of executing the next processing of the CPU 1 just after the cache hit access is completed, and a read data register 10 inside the CPU 1 is rewritten.


Inventors:
Yamamoto, Masaaki
Hisada, Yoshiaki
Application Number:
JP1993000114606
Publication Date:
November 25, 1994
Filing Date:
May 17, 1993
Export Citation:
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Assignee:
HITACHI LTD
HITACHI NISHI SERVICE ENG:KK
International Classes:
G06F12/08; G06F12/16; (IPC1-7): G06F12/08; G06F12/16