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Title:
MALFUNCTION PREVENTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6451819
Kind Code:
A
Abstract:

PURPOSE: To prevent an output of erroneous pulse at unstable period of a logic circuit by bypassing an output signal for an unstable period outputted from a logic circuit while turning on a transistor(TR).

CONSTITUTION: In applying a power supply Vcc, a logic circuit 21 is unstable and an erroneous pulse tends to be outputted, but a current flows between a resistor 4 and the 1st TR 2, which is turned on to absorb an erroneous pulse. Thus, an output TR 26 is turned off and not affected by the erroneous pulse. When the current Vcc is made stable, the 2nd TR 3 is turned on, the 1st TR 2 is turned off and the pulse outputted from the logic circuit 1 after it is made stable is given to the output TR 26. Thus, the mis-output of the logic circuit at the unstable period is prevented surely with simple constitution.


Inventors:
NAGAHISA TETSURO
TANAKA YUJI
IMAI HIDETOSHI
Application Number:
JP20968087A
Publication Date:
February 28, 1989
Filing Date:
August 24, 1987
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03K17/22; H03K5/08; (IPC1-7): H03K5/08; H03K17/22
Domestic Patent References:
JPS56166637A1981-12-21
Attorney, Agent or Firm:
Akira Kobiji (2 outside)



 
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