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Patent Searching and Data


Title:
MANUFACTURE OF BI-CMOS INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS631048
Kind Code:
A
Abstract:

PURPOSE: To resist a soft-error to α-rays, to thin an epitaxial laver and to increase working speed by forming an N-type buried layer to a P-type substrate, shaping a P-type buried layer into the buried layer and growing the epitaxial layer onto these substrate and buried layers.

CONSTITUTION: A first N-type buried layer 2 having high resistance and a deep junction and a second N-type buried layer 3 having low resistance and a shallow junction are formed in regions in which each of N channel type and P channel type transistors is shaped in a P-tyre substrate, and P-type buried layers 4 are formed to the layer 2 and a bipolar element isolation region. when an N-type epitaxial layer 5 is shaped onto these layers and a P-type well layer 6 is formed, the P-type well layer in the N channel transistor is formed to an insular shape surrounded by the N-type buried layer and the N-type epitaxial layer. and resists against a soft-error by α-rays while the P-type well layers are deepened substantially without thickening the N-type epitaxial layer by the layers 4 and withstanding voltage thereof is increased. A bipolar transistor is operated at high speed without lowering withstanding voltage by the thin N-type epitaxial layer.


Inventors:
SAWADA SHIGEKI
Application Number:
JP14533686A
Publication Date:
January 06, 1988
Filing Date:
June 20, 1986
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L27/06; H01L21/8249; (IPC1-7): H01L27/06
Attorney, Agent or Firm:
Toshio Nakao