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Title:
MANUFACTURE OF COMPLEMENTARY INSULATING GATE ELECTRIC FIELD EFFECT SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5460867
Kind Code:
A
Abstract:

PURPOSE: To increase the integral density by removing the insulating film formed on the semiconductor substrate on the channel forming region, coating there the lamination film comprising the insulating film and the acid-proof film newly and then formimg the P- and N-type channel source and drain regions through diffusion with the opening provided.

CONSTITUTION: P-type well region 31 is formed through diffusion to N-type Si substrate 30 with SiO2 film 32 covering over the entire surface, and film 32 is removed through etching on the soruce and drain forming regions at both channels of the complementary circuit. Then acid-proof film 34 such as Si3N4 or the like is coated there via thin SiO2 film 33 with the opening provided on the P-channel transistor forming region to form P-type source and drain regions 35 and 36 plus P+ -type region 37 covering over region 31 through diffusion. After this, N-type guard ring 40 is provided at both sides sandwiching region 35 and 36. At the same time, N-type source and drain regions 38 and 39 of the N-channel transistor are formed through diffusion within P-type well region 31. As a result, the chip area can be reduced


Inventors:
MATSUKUMA MOICHI
HOSHI TOSHIAKI
Application Number:
JP12801677A
Publication Date:
May 16, 1979
Filing Date:
October 24, 1977
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L29/78; H01L21/22; H01L21/8238; H01L27/092; (IPC1-7): H01L21/22; H01L29/06; H01L29/78
Domestic Patent References:
JPS52117589A1977-10-03
JPS5197388A1976-08-26
JPS50138769A1975-11-05
JPS5084185A1975-07-07



 
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