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Title:
MANUFACTURE OF FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPS6189678
Kind Code:
A
Abstract:

PURPOSE: To obtain a field effect transistor realizing high mutual conductance even at a deep bias near its pinch off and allowing low noise operation.

CONSTITUTION: An active layer 2 is made to grow on a substrate 1 and a carri er density varying region 3 is innevitably formed in an interface between the substrate 1 and the active layer 2. Next, an Al layer 4 is thickly evaporated on the surface of the active layer 2 and then the substrate 1 is removed by etching to expose the active layer 2. Next, on the back of the exposed active layer 2, that is, the interface on the side on which crystal grow previously, a gat electrode 5, a source electrode 6 and a drain electrode 7 are provided. In the field effect transistor constituted in this way, a channel formed by a gate depletion layer 8 and an interface depletion layer 9 is in a region where its carrier density is constant even at the bias condition just before the pinch off and a desired mutual conductance can be, therefore, realized.


Inventors:
KAZUMURA MASARU
HAGIO MASAHIRO
NISHIUMA MASAHIRO
OOTA KAZUNARI
KANAZAWA KUNIHIKO
GODA KAZUHIDE
TSUKADA KOJI
KATSU SHINICHI
Application Number:
JP21044684A
Publication Date:
May 07, 1986
Filing Date:
October 09, 1984
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L29/812; H01L21/338; H01L29/423; (IPC1-7): H01L29/80
Attorney, Agent or Firm:
Koji Hoshino



 
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