MANUFACTURE OF FIELD EFFECT TRANSISTOR

Title:

MANUFACTURE OF FIELD EFFECT TRANSISTOR

Document Type and Number:

Japanese Patent JPS63126280

Kind Code:

A

Abstract:

PURPOSE: To absorb the damage caused by dry etching process indispensable for arrangeing an gate electrode having a vertical side surface, by forming an electrically inactive region, that is, an insulative layer on a conductive semiconductor layer.

CONSTITUTION: Conductive semiconductor 2, WSi 3, and low resistance metal W 4 are formed on the surface of a GaAs semiconductor substrate 1. Thereon a photoresist layer 5 is formed leaving only a part where a gate electrode is formed, and then the gate electrode 7 is formed. Next, after a photoresist layer 8 is formed, ions are implanted, and a protrusion 10 is formed at the bottom of the conductive semiconductor layer 2 corresponding with an electrically inactive region 9. After a sidewall 12 is formed, ions are implanted, and a low impurity concentration region 14 and a high impurity concentration regions 15 are formed. Next, an ohmic electrode 20 is formed and an FET 21 is completed.

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Inventors:

SHIMADA CHO
AKIYAMA TATSUO
ETSUNO YUTAKA

Application Number:

JP27177486A

Publication Date:

May 30, 1988

Filing Date:

November 17, 1986

Export Citation:

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Assignee:

TOSHIBA CORP

International Classes:

H01L21/31; H01L21/265; H01L21/338; H01L29/80; H01L29/812; (IPC1-7): H01L21/265; H01L21/31; H01L29/80

Attorney, Agent or Firm:

Norio Ogo (1 outside)

Previous Patent: JPS63126279

Next Patent: JPS63126281