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Title:
MANUFACTURE OF FLAT-PANEL FED SCREEN, AND FLAT-PANEL FED SCREEN
Document Type and Number:
Japanese Patent JP10188785
Kind Code:
A
Abstract:

To provide a manufacturing method enabling a microchip to be formed at a far small cost using a general microelectronics technique and facility.

A structure 14 of a charge emitting material defining the cathode of a flat-panel FED screen and orienting the grid of its screen has a part 16 that is a tubular body with a small radius of curvature. The structure 14 is obtained by forming an opening in a dielectric layer 6 separating a first conductive layer 3 and a resistance layer 5 from a second conductive layer 8, depositing a layer of a conductive material and a conductive layer which cover the wall of the opening, and etching anisotropically the layer of conductive material for removal of the layer of conductive material from the upper end of the wall-covering part so that an inwardly inclined edge 16 equipped with the part 16 serving as an emission chip is formed. Thereafter, the part of the dielectric layer 6 surrounding the structure 14 is removed.


Inventors:
Baldi, Livio
Marangon, Maria Santina
Application Number:
JP1997000271094
Publication Date:
July 21, 1998
Filing Date:
October 03, 1997
Export Citation:
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Assignee:
SGS THOMSON MICROELECTRON SRL
International Classes:
H01J1/304; H01J9/02; H01J29/04; H01J31/12; H01L29/66; H01J1/30; H01J9/02; H01J29/04; H01J31/12; H01L29/66; (IPC1-7): H01J9/02; H01L29/66