Title:
MANUFACTURE OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH04233225
Kind Code:
A
Abstract:
PURPOSE: To provide a method which enables etching, without damaging a shape characteristics portion on a lower part of a planarized insulating layer so as to form an aperture. CONSTITUTION: Double insulating layers (for example, 33 and 35) are formed to cover an active region of a transistor and a protruding shape characteristic portion such as a gate runner (for example, 31). The upper insulating layer (for example, 35) is planarized, thus further facilitating subsequent secondary work of a multilayer conductor. By etching which penetrates the upper insulating layer (for example, 35) and stops at the lower insulating layer (for example, 33), windows (for example, 43 and 41) are opened in the double insulating layers. After that, etching processing is continued, and etching is carried out so as to penetrate the lower insulating layer (for example, 33).
Inventors:
DEBITSUDO POORU FUABUROU
JIEEN AN SUIDERUSUKII
DANIERU JIYOSEFU BIITOKABEEJI
JIEEN AN SUIDERUSUKII
DANIERU JIYOSEFU BIITOKABEEJI
Application Number:
JP16528591A
Publication Date:
August 21, 1992
Filing Date:
June 11, 1991
Export Citation:
Assignee:
AMERICAN TELEPHONE & TELEGRAPH
International Classes:
H01L21/28; H01L21/302; H01L21/3065; H01L21/311; H01L21/316; H01L21/768; (IPC1-7): H01L21/28; H01L21/302; H01L21/312; H01L21/90
Domestic Patent References:
| JPH01304725A | 1989-12-08 | |||
| JPS6448425A | 1989-02-22 | |||
| JPS6435960A | 1989-02-07 | |||
| JPH0258353A | 1990-02-27 | |||
| JPH01169931A | 1989-07-05 | |||
| JPS6425545A | 1989-01-27 | |||
| JPH01241135A | 1989-09-26 |
Attorney, Agent or Firm:
Hirofumi Mimata
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