Title:
MANUFACTURE FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5489594
Kind Code:
A
Abstract:
PURPOSE:To increase the degree of integration and also to improve the yield rate, by providing all the openings required for the wiring formation with the self-alignment method using the acid proof material such as Si3N4, when the polycrystal Si film is constituted with IGFET used for the gate electrode material. CONSTITUTION:The active region of P type Si substrate 101 is oxidized under water vapor by covering it with the Si3N4 film 103, and thick field SiO2 film 102 is caused other than the active region. Next, the film 103 for the other part is removed by leaving a part of the film 103 used for diffusion, and the gate SiO2 film 104, polycrystal Si film 105 and Si3N4 film are laminated and coated on the entire surface. After that, the film 106 is left only on the gate region and the film 102, and the film 104 and 105 on the diffusion region 107 are removed by etching. Further, the region 107 is formed by diffusion N type impurity in the substrate 101 exposed, the entire surface is covered with the SiO<2> film 108, and the wiring electrode 109 is fitted by opening the open hole.
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Inventors:
KUDOU OSAMU
Application Number:
JP15885277A
Publication Date:
July 16, 1979
Filing Date:
December 27, 1977
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L29/78; H01L21/306; H01L21/768; H01L23/522; (IPC1-7): H01L21/306; H01L21/90; H01L29/78
Domestic Patent References:
| JPS51112193A | 1976-10-04 |