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Patent Searching and Data


Title:
MANUFACTURE OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS641235
Kind Code:
A
Abstract:

PURPOSE: To effectively detect the exposure time of a base pattern surface at the time of finishing etching of upper layer to be etched of an uppermost layer film by forming in advance a thin film containing element or molecule having preferable analysis sensitivity on the base pattern surface, and analyzing the element or molecules contained in the film to detect the exposure of the base pattern surface when the upper layer to be etched is etched.

CONSTITUTION: After a film is formed of a base pattern material 2 during etching, a thin film 3 containing element or molecules having preferable analysis sensitivity. After a resist pattern 5 is then formed, with it as a mask the material 2 and the film 3 are patterned. Then, an upper layer 4 to be etched formed on the pattern 2 and the film 3, and a resist pattern 5' is formed thereon. With the pattern 5' as a mask the layer 4 is selectively etched. In this case, etching conditions are so set as to similarly etch the film 3 to the layer 4. Thus, a time when the etching arrives at the base pattern surface is detected by analyzing the element or the molecules, thereby effectively finishing the etching.


Inventors:
NODA MINORU
Application Number:
JP15706187A
Publication Date:
January 05, 1989
Filing Date:
June 23, 1987
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/302; H01L21/3065; (IPC1-7): H01L21/302
Attorney, Agent or Firm:
Masuo Oiwa