MANUFACTURE OF JUNCTION TYPE FET - YOKOGAWA ELECTRIC CORP

Title:

MANUFACTURE OF JUNCTION TYPE FET

Document Type and Number:

Japanese Patent JPS644079

Kind Code:

A

Abstract:

PURPOSE: To make position alignment between a gate electrode and a p+ diffusion region needless to upgrade integrity, by diffusing p-type impurities from a gate electrode to a semiconductor substrate just under the gate electrode.

CONSTITUTION: After a gate electrode 7 is selectively formed on a surface of an (n) layer, ramp annealing is performed to diffuse p-type impurities from the gate electrode 7 to the (n) layer 2 just under the gate electrode 7 so that a p+ diffusion region 8 is formed. A pn junction is thus formed between the (n) layer 2 and the p+ diffusion region 8. The p+ diffusion region 8 of a junction type FET composed in this way is formed with the gate electrode 7 as a diffusion source, and so fine processing can be realized sufficiently according to precision in the processing of the gate electrode 7, and also integrity can be upgraded.

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Inventors:

YAGIHARA TAKESHI
MATSUDA HIROFUMI
KOBAYASHI SHINJI
MIURA AKIRA

Application Number:

JP15907487A

Publication Date:

January 09, 1989

Filing Date:

June 26, 1987

Export Citation:

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Assignee:

YOKOGAWA ELECTRIC CORP

International Classes:

H01L21/26; H01L21/225; H01L21/28; H01L21/337; H01L29/80; H01L29/808; (IPC1-7): H01L21/225; H01L21/26; H01L21/28; H01L29/80

Domestic Patent References:

JPS60220975A

1985-11-05

Attorney, Agent or Firm:

Shinsuke Ozawa

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