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Title:
MANUFACTURE OF MIS TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH01122162
Kind Code:
A
Abstract:

PURPOSE: To simplify a process by forming a high-concentration source-drain region, using an oxidation-resistant material layer laminated onto a gate electrode material layer as a mask, oxidizing the outside of a gate electrode section and shaping a low concentration source-drain region, employing a gate electrode as a mask.

CONSTITUTION: An oxidizing gate-electrode material layer 31 and an oxidation- resistant material layer 8 are laminated successively onto one surface of a first conductivity type semiconductor substrate 1 on which an oxidation-resistant gate insulating film 2 is applied. Both layers 31, 8 are patterned in specified size larger than an expected gate electrode size, and a second conductivity type high-concentration source-drain region 6 is shaped by introducing an impurity, using both layers patterned as masks. A gate-electrode external section in the gate-electrode material layer 31 is oxidized, and the oxidation-resistant material layer 8 and a gate-electrode material layer oxidizing section 32 are removed. A second conductivity type low-concentration source-drain region 5 is formed by introducing an impurity, employing a gate electrode 3 left as a mask. Accordingly, processes are simplified.


Inventors:
SUGAHARA NORIYUKI
Application Number:
JP27967487A
Publication Date:
May 15, 1989
Filing Date:
November 05, 1987
Export Citation:
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Assignee:
FUJI ELECTRIC CO LTD
International Classes:
H01L21/336; H01L29/78; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Iwao Yamaguchi



 
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