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Patent Searching and Data


Title:
MANUFACTURE OF MOS SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH06151452
Kind Code:
A
Abstract:

PURPOSE: To obtain the manufacturing method of a MOS semiconductor device having a DI-LDD structure in which the fluctuation of the threshold or deterioration of the current driving ability is suppressed or a pocket structure.

CONSTITUTION: The title method involves a process for forming a gate insulating film 3 on a P-type semiconductor substrate 1 and P-type channel impurity area 4 in a channel area, process for forming a gate electrode 5 and N-type low- concentration LDD diffusion layer 6 by using the electrode 5 as a mask, process for forming side walls 7 on both sides of the electrode 5 and P-type punch- through stopper areas 8 by using the walls 7 as masks, and process for forming an N-type high-concentration source-drain areas 9. Since the side walls 7 are utilized for injection at the time of forming the stopper areas 8, the influence of the areas 8 to the impurity area 4 can be prevented and the fluctuation of the threshold or deterioration of the current driving ability can be prevented.


Inventors:
TAKAHASHI SANEKATSU
Application Number:
JP31623392A
Publication Date:
May 31, 1994
Filing Date:
October 31, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/265; H01L21/336; H01L29/78; (IPC1-7): H01L21/336; H01L21/265; H01L29/784
Attorney, Agent or Firm:
Suzuki Akio