Title:
MANUFACTURE OF MOSSTYPE SEMICONDUCTOR
Document Type and Number:
Japanese Patent JPS5451785
Kind Code:
A
Abstract:
PURPOSE:To increase the degree of integration by eliminating the overlap margin between the gate electrode and the field isolation layer as well as to secure the facilitated multi-layer wiring through effective combinations of electrodes. CONSTITUTION:An opening is provided to gate insulating film 302 on P-type Si301, and conductive poly Si304 is coated. Then an opening is drilled to layer 304 via SI3N4 mask 305, and the impurity is added to substrate 301 to avoid the parasitic MOS and to form oxide thin film 307. Mask 305 is then removed, and W-mask 308A and 308B are formed selectively, and then gate electrode 304A and B plus gate film 302A and B are formed via the W-mask. Overlap margin l1 is secured at first between electrode 308A and film 307 in consideration of the mask shift, and only the electrode is removed as if it were pulled back by l2 after formation of the gate region in order to eliminate the over- lap. After this, source/drain 309A-312A are formed as usual with the electrode attached. The gate electrode can be utilized to the wiring material since the high fusing point metal is used, thus the formation of the multi-layer wiring becomes easy. Furthermore, a high integration can be obtained because the overlap margin is eliminated.
Inventors:
YOSHIDA HIROYUKI
Application Number:
JP11785477A
Publication Date:
April 23, 1979
Filing Date:
October 03, 1977
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H01L21/8234; H01L21/306; H01L21/3205; H01L23/52; H01L27/04; H01L27/088; H01L29/78; (IPC1-7): H01L21/90; H01L27/04; H01L29/78
Domestic Patent References:
| JPS51145285A | 1976-12-14 | |||
| JPS5261960A | 1977-05-21 |
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