Title:
MANUFACTURE OF MULTICHIP MODULE
Document Type and Number:
Japanese Patent JP3630777
Kind Code:
B2
Abstract:
PURPOSE: To form current-carrying paths having a layer composed of a buried dielectric substance and further a specific aspect ratio, by forming the current- carrying paths in trenches by currentless metal deposition.
CONSTITUTION: Dielectric with a permittivity of ≤3 is applied to a non- conductive substrate, and is subjected to heat treatment (a). Next TSI resist is applied to the dielectric (b), and the resist is exposed in order to form current- carrying paths (c). Then a structure obtained by turning the resist into silyl (d) is migrated into the dielectric (e), and a seed layer is formed on the structured surface. Then the resist is removed to form trenches with an aspect ratio of ≥1 (g), and current-carrying paths are formed by currentless metal deposition (h). After dielectric is placed on the flat surface (i), resist is applied to the dielectric (j), and then the resist is exposed in order to form through holes (k). Then a structure obtained by turning the resist into silyil (1) is migrated into the dielectric (m), and then the through holes are formed (n).
Inventors:
Liner Roy Schüner
Helmut Arne
Siegfried Birkle
Albert hammer hammer
Lekai Zechi
Tobias Nor
Andumulin
Helmut Arne
Siegfried Birkle
Albert hammer hammer
Lekai Zechi
Tobias Nor
Andumulin
Application Number:
JP17688195A
Publication Date:
March 23, 2005
Filing Date:
June 21, 1995
Export Citation:
Assignee:
Siemens Aktiengesellschaft
International Classes:
G03F7/075; C23C14/20; G03F7/26; H01L21/48; H01L21/768; H01L23/52; H05K3/02; H05K3/10; H05K3/46; H05K3/00; H05K3/04; H05K3/18; H05K3/38; (IPC1-7): H05K3/46; C23C14/20; G03F7/075; G03F7/26; H05K3/10
Domestic Patent References:
| JP246463A | ||||
| JP2151030A | ||||
| JP4168730A | ||||
| JP5303210A | ||||
| JP3188447A | ||||
| JP3147314A | ||||
| JP1186936A |
Foreign References:
| US5108785 |
Attorney, Agent or Firm:
Iwao Yamaguchi