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Patent Searching and Data


Title:
MANUFACTURE OF MULTILAYER INTERCONNECTION BOARD
Document Type and Number:
Japanese Patent JPH02278732
Kind Code:
A
Abstract:

PURPOSE: To eliminate improper connection of conductor patterns formed on the upper and lower surfaces of an interlayer insulating film by forming through-holes in which the opening of the upper surface is concentric with that of the lower surface, and removing the unnecessary part of an insulating layer from the upper surface of the insulating layer in depth not passing its thickness direction by isotropically removing means.

CONSTITUTION: An unnecessary part 11 passing an insulating layer 3 by utilizing a first resist mask at an interlayer insulating film 3 covering an insulating substrate 1 formed with a conductor pattern 2 is removed by etching of isotropically removing means, an unnecessary part 12 is then removed in a suitable depth around the unnecessary part 11 from the upper surface of the layer 3 by using a second resist mask by etching of isotropically removing means, a stepped through-hole 13 is formed, and it is then covered with a conductor layer 5. That is, the through-hole provided at the insulating layer has a smaller opening of the lower surface than that of the upper surface of the insulating layer and is formed in a tapered state smoothly narrowed at the lower part. Thus, the conductor layer covering the insulating layer is formed relatively thickly also on the sidewall of the through hole, and effectively electrically connected to the conductor pattern formed under the insulating layer.


Inventors:
YONEHARA HIROYUKI
Application Number:
JP9932689A
Publication Date:
November 15, 1990
Filing Date:
April 19, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/3205; (IPC1-7): H01L21/3205
Attorney, Agent or Firm:
Sadaichi Igita