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Title:
MANUFACTURE OF P-N-P TRANSISTOR
Document Type and Number:
Japanese Patent JPS59158556
Kind Code:
A
Abstract:

PURPOSE: To shorten the time of manufacture, and to prevent erroneous operation in a mask alignment, etc. by forming a manufacturing process for a base and an emitter in a P-N-P transistor by one mask.

CONSTITUTION: A silicon oxide film 2 containing a P type impurity is formed on a P type silicon substrate 1, a nitride film 3 is formed on the film 2, and a photo-resist 4 is applied on the film 3. A pattern is baked onto the photo-resist 4 by a mask 5, and a window 6 is bored. Hot phosphoric acid is applied from the upper section of the window 6, and a window 7 is bored to the nitride film 3. The silicon oxide film 2 is etched by fluoric acid. The photo-resist is removed, and an N type impurity 9 is deposited in a window 8. The N type impurity 9 creeps into the window 7 of the nitride film 3 owing to a gas at that time. When the N type impurity 9 is diffused, the P type impurity in the silicon oxide film 2 is also diffused simultaneously, and N type base layer 10 and P layer 11 are formed on the P type silicon substrate 1 at the same time. A window 13 is bored onto the oxide film 12 while using the nitride film 3 as a mask, and the P type impurity is deposited and diffused from the window 13 to form a P emitter layer 14 on the base layer 10.


Inventors:
KATAOKA MASASHI
Application Number:
JP3238483A
Publication Date:
September 08, 1984
Filing Date:
February 28, 1983
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
H01L29/73; H01L21/331; H01L29/72; (IPC1-7): H01L29/72
Attorney, Agent or Firm:
Toshimaru Takemoto



 
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