Title:
MANUFACTURE OF PMOS, AND MANUFACTURE OF CMOS
Document Type and Number:
Japanese Patent JP3420879
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide the manufacture of CMOS where both n MOS and p MOS can operate at high speed, and further short channel effect is hard to occur in the p MOS.
SOLUTION: A p well 13a and an n well 13b are made on a silicon substrate 11. Next, punch through suppression implantation and channel implantation are performed for a region 17a, and punch through suppression implantation is performed for a region 17b. Next, silicon films 19a and 19b are made by epitaxial growth on the surface of the silicon substrate of this sample. The silicon films 19a1 and 19b1 in the first stage are made in thickness of 10nm on condition that the concentration of boron within the film becomes, for example, about 2.4×1018cm-3, and the silicon films 19a2 and 19b2 in the second stages are grown in thickness of 10-40nm on condition that the concentration of boron within the film becomes, for example, about 2.4×1018cm-3. Then, after formation of gate electrodes 27a and 27b, a source and a drain are made.
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Inventors:
Hideaki Matsuhashi
Application Number:
JP4920696A
Publication Date:
June 30, 2003
Filing Date:
March 06, 1996
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H01L29/78; H01L21/8238; H01L27/092; (IPC1-7): H01L29/78; H01L21/8238; H01L27/092
Domestic Patent References:
| JP7161974A | ||||
| JP6236967A | ||||
| JP5243568A |
Attorney, Agent or Firm:
Kenji Ohnishi