Title:
MANUFACTURE OF RECESSED GATE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS62262468
Kind Code:
A
Abstract:
A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. Parallel grooves are etched through the low resistivity N-type layer into the high resistivity N-type layer forming interposed ridges of silicon. When fabricating junction gate devices, P-type zones are formed at the end walls of the grooves by ion implantation. A layer of silicon oxide is formed on the side walls of the grooves exposing the silicon at the end walls of the grooves and at the surfaces of the ridges. A layer of a silicide-forming metal, specifically cobalt, is deposited. A rapid thermal annealing treatment is performed which causes the cobalt to react with the silicon and form cobalt silicide at the cobalt-silicon interfaces. The cobalt does not react with the silicon oxide at the side walls of the grooves. The unreacted cobalt is removed by an etching solution which does not attack the cobalt silicide. Metal layers are placed on the cobalt silicide to increase its conductivity as contact members.
Inventors:
EMERU ESU BIYURATSUTO
BURAIAN EMU DEITSUCHIEKU
SUKOTSUTO JIEI BATORAA
BURAIAN EMU DEITSUCHIEKU
SUKOTSUTO JIEI BATORAA
Application Number:
JP10650187A
Publication Date:
November 14, 1987
Filing Date:
May 01, 1987
Export Citation:
Assignee:
GTE LABORATORIES INC
International Classes:
H01L21/28; H01L21/285; H01L21/335; H01L29/10; H01L29/43; H01L29/47; H01L29/772; H01L29/80; (IPC1-7): H01L21/28; H01L29/80
Attorney, Agent or Firm:
Motohiro Kurauchi