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Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE HAVING MULTILAYER INTERCONNECTION STRUCTURE
Document Type and Number:
Japanese Patent JPH07147279
Kind Code:
A
Abstract:

PURPOSE: To omit a resist coating process to take a labor hour by a method wherein a treating process using oxygen plasma and an etching process using a buffered hydrofluoric acid liquid are added after an etchback process ends.

CONSTITUTION: A BPSG film 2 and an SOG film 3 are laminated and formed on a lower wiring layer 1 to form into an interlayer insulting film 4. Then, the film 3 is etched back and residual SOG films 3a are respectively deposited on the end parts of the film 2. The films 3a and the film 2 are exposed to an oxygen plasma atmosphere to improve an etching selectivity. Moreover, a buffered hydrofluoric acid treatment is performed to remove the films 3a and after that, an upper wiring layer 6 is formed on the film 2. Accordingly, a resist coating process to take a labor hour can be omitted and a treating time can be shortened.


Inventors:
HIRATA TADASHI
Application Number:
JP29230093A
Publication Date:
June 06, 1995
Filing Date:
November 24, 1993
Export Citation:
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Assignee:
KAWASAKI STEEL CO
International Classes:
H01L21/302; H01L21/3065; H01L21/316; H01L21/3205; (IPC1-7): H01L21/3205; H01L21/3065; H01L21/316
Attorney, Agent or Firm:
Eiichi Kobayashi



 
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