MANUFACTURE OF SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE

Japanese Patent JP2000332100

A

To prevent generation of shortcircuits due to contact between a bonding wire and a metallic layer by forming a metallic layer selectively inside an isolation groove through an electroless plating method using a catalyst layer, formed in a bottom inside an isolation groove and forming an upper end of a metallic layer lower than an end part of an opening part of an isolation groove.

A catalyst layer 3 on a photoresist layer 2 is removed, and the catalyst layer 3 is left selectively only at the bottom of a first isolation groove 1a. When a GaAs substrate 1 is immersed in an Ni-electroless plating solution, since the rear and the side of the GaAs substrate 1 are far from the catalyst layer 3 which is generated source for atomic hydrogen, hydrogen is not supplied. Therefore, a plating layer is not formed, and an Ni-plating layer 4 can be selectively formed only in an area near the catalyst layer 3, whereto atomic hydrogen is supplied. Thereby, the upper end of the Ni-plating layer 4 is lower than an end part of an opening part 1a, and shortcircuit to the Ni- plating layer 4 can be prevented, even when the surface of the GaAs substrate 1 is subjected to wire bonding.

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OZAKI KATSUYA
NAKANO HIROBUMI
KUNII TETSUO

JP13712499A

November 30, 2000

May 18, 1999

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MITSUBISHI ELECTRIC CORP

H01L21/301; H01L21/68; H01L23/367; H01L21/288; H01L21/78; (IPC1-7): H01L21/76; H01L21/301; H01L21/822; H01L27/04

Aoyama Ryo (1 person outside)

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