Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2838992
Kind Code:
B
Abstract:
PROBLEM TO BE SOLVED: To enable even an upper insulating film on a wiring to be widely flattened by a method wherein voids present inside the insulating film are exposed in grooves by chemical-mechanical polishing, and a spin-on-glass film is applied to fill the grooves.
SOLUTION: When an insulating film 113 is applied onto wirings 112 narrow in pitch between them, voids 114 are produced in the film 113 as the film 113 is not enough in fluidity. The surface of the insulating film 113 is chemically and mechanically polished from above, the voids 114 are turned into grooves 114-1 and 114-2 cut in the surface of the insulating film 113, and the insulating film 113 is dry-etched back so as to make the openings of the grooves 114-1 and 114-2 wide. Then, a spin-on-glass SOG film 116 is applied onto the insulating film 113 by spin coating, and the SOG film 116 and the insulating film 113 are dry-etched at a constant speed. The SOG film 116 is completely removed front the flat part of the insulating film 113, and the SOG film is left unremoved only inside the grooves 114-1 and 114-2. An insulating film 115 is formed on the flat plane 117 to fully cover the SOG film in the grooves so as to prevent the SOG film from being removed in an upper wiring forming process.
Inventors:
Sakao, Masato
Takaishi, Yoshihiro
Takaishi, Yoshihiro
Application Number:
JP1995000293088
Publication Date:
October 16, 1998
Filing Date:
November 10, 1995
Export Citation:
Assignee:
NEC CORP
International Classes:
H01L21/302; H01L21/304; H01L21/3065; H01L21/3105; H01L21/316; H01L21/3205; H01L21/768; (IPC1-7): H01L21/3205; H01L21/768
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