Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3613838
Kind Code:
B2
Abstract:
PURPOSE: To manufacture easily a semiconductor device having a protective cap by a method wherein with a bonding frame consisting of a silicon thin film patterned on the periphery of an element formation region on the surface of a silicon wafer, a bonding layer consisting of a gold film is patterned on a wafer for cap formation and both wafers are bonded together.
CONSTITUTION: A bonding frame 21 consisting of a silicon thin film is patterned on the periphery of an element formation region on the surface of a silicon wafer (a semiconductor wafer) 32 for movable gate MOS transistor (sensor element) formation and at the same time, a bonding layer 24 consisting of a gold film is patterned on a part, which corresponds to a bonding frame pattern, of a silicon wafer 33 for cap formation. Then, the frame 21 on the wafer 32 and the layer 24 on the wafer 33 are heated at a temperature higher than a gold/silicon eutectic temperature in a state that the frame 21 comes into contact with the layer 24 to bond the frame 21 to the layer 24 and both wafers 32 and 33 are diced in every chip.
Inventors:
Fumio Ohara
Shinji Yoshihara
Katsuhiko Kanamori
Takashi Kurahashi
Shinji Yoshihara
Katsuhiko Kanamori
Takashi Kurahashi
Application Number:
JP12013895A
Publication Date:
January 26, 2005
Filing Date:
May 18, 1995
Export Citation:
Assignee:
株式会社デンソー
International Classes:
H01L29/84; B29C43/36; B81C1/00; G01P1/02; G01P15/08; G01P15/12; H01L21/301; H01L21/822; H01L23/053; H01L23/10; H01L27/04; (IPC1-7): H01L21/301; H01L21/822; H01L27/04; H01L29/84
Domestic Patent References:
| JP6347475A | ||||
| JP62054969A | ||||
| JP7110341A | ||||
| JP6213747A |
Attorney, Agent or Firm:
Hironobu Onda
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