PURPOSE: To accelerate the operational rate by a method wherein the second conductivity type silicon epitaxial layer is selectively epitaxial-deposited in the lateral direction from the edge of the second insulating film.

CONSTITUTION: Resorting to the manufacturing process of bipolar transistors, the resistance of a base extraction electrode can be lowered by forming a thin silicon epitaxial layer 13 to form a base layer and exposing the base extraction electrode as well as depositing another thick silicon epitaxial layer 15. Furthermore, the silicon epitaxial layer 15 is deposited in the lateral direction as if covering the peripheral surface of a nitride film 14 so that the fine emitter region 18 hardly formed by the lithography may be formed in selfalignment with the opening width thereof controlled in excellent reproducibility. Through these procedures, the base resistance can be lowered even in the thin base layer with the emitter region miniaturized, thereby enabling the operational rate to be accelerated.