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Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH07201972
Kind Code:
A
Abstract:

PURPOSE: To form a fine element isolation region and a relatively wide element isolation region uniformly and flatly.

CONSTITUTION: On a silicon-on-insulator semiconductor substrate 14 which is formed by an SIMOX technology so as to have a silicon oxide film layer 15 buried in an ordinarily used silicon substrate as shown in the Fig. (a), a photoresist pattern 8 as shown in the Fig. (b) is formed. Dry-etching is performed with the photoresist pattern 8 as a mask to form trenches 16 which reach the buried silicon oxide film layer 15 from the surface and the buried silicon oxide film layer 15 is exposed. The substrate 14 is dipped into solution 12 of silicon dioxide dissolved in silicificated hydrofluoric acid as shown in the Fig. (c) and boric acid solution is dropped to deposite silicon dioxide only on the parts of the oxide film layer 15 exposed in the trenches 16 selectively and the silicon oxide film is made to grow to have a thickness not smaller than the thickness of the silicon substrate 14 and the trenches 16 are filled with the silicon oxide film 17.


Inventors:
KAWAGUCHI MASATERU
Application Number:
JP33664593A
Publication Date:
August 04, 1995
Filing Date:
December 28, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/762; H01L21/76; H01L27/12; (IPC1-7): H01L21/76; H01L21/762; H01L27/12
Domestic Patent References:
JPH06204332A1994-07-22
JPH0661343A1994-03-04
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)