Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0997796
Kind Code:
A
Abstract:
To prevent a check pattern from being deformed in a photolithography process.
For instance, a first wiring layer 5-1, a BPSG film 4, and a field oxide film 2-2 are formed under a through-hole main scale pattern 7-2A and a resist vernier scale pattern 9-2A used for reading deviation in a lithography process where a second wiring conductive film 8 is patterned, whereby a pattern is protected against deformation caused by defocus of the resist vernier scale pattern 9-2A.
Inventors:
ARITOKU TAKEHIRO
Application Number:
JP25153395A
Publication Date:
April 08, 1997
Filing Date:
September 28, 1995
Export Citation:
Assignee:
NEC CORP
International Classes:
H01L21/3213; H01L21/027; (IPC1-7): H01L21/3213; H01L21/027
Domestic Patent References:
| JPH0574769A | 1993-03-26 |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
Next Patent: FORMING METHOD OF LAMINATED WIRING