Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS55107244
Kind Code:
A
Abstract:
PURPOSE:To increase integration degree by a method wherein a poly-Si layer uniformly formed is selectively etched to form a thin layer portion and a highly resistance element in that portion. CONSTITUTION:An element isolating region 23 is made by selectively oxidizing a Si substrate 21, and a poly-Si layer 24 is accumulated on the substrate after the formation of an oxide gate film. Next by providing a resist mask 25, ion injection is added to the surface layer while selecting the quantity of addition and energy. If the mask is removed and plasma etching is added, a thin layer portion can be made selectively in the ion-injected portion by means of difference in etching speed. The surface is then etched while providing a resist mask 26 so as to make a window selectively in the poly-Si layer 24. By this method, it is possible to control the quantity of injection ions and form a thin poly-Si layer with the resistance value desired readily and accurately in the region specified.
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Inventors:
NAGAKUBO YOSHIHIDE
Application Number:
JP1387379A
Publication Date:
August 16, 1980
Filing Date:
February 09, 1979
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L27/04; H01L21/3205; H01L21/822; H01L23/52; (IPC1-7): H01L21/88; H01L27/04