Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS58143549
Kind Code:
A
Abstract:
PURPOSE:To prevent the generation of a parasitic channel in an element isolation by etching the side surface of the groove of the element isolation region so as to region form an inclined plane with the tilt angle of 45 deg.-80 deg. to the surface of a substrate, burying an insulating film into the groove and flattening the groove. CONSTITUTION:A mask 22 is fomed onto the surface of the silicon substrate 21, and the groove 23, the tilt angle theta of the side surface thereof is 45 deg.-80 deg., is formed into the element isolation region through reaction ion etching. The ions of an impurity with a conduction type the same as the substrate are implanted by using the same mask 22. In this case, an ion implantation layer 24 is formed not only on a bottom surface but also on the side surface at the same time because the side surface of the groove 24 forms the inclined plane. An oxide film can be buried into the isolation region in a flat shape extending over the whole surface of the substrate through a process the same as a conventional method. As its embodiment, ions can be implanted simultaneously to the bottom surface and side surface of the isolation region by ion implantation at a time by sloping the side surface of the isolation region, and the generation of the parasitic channel can be prevented.
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Inventors:
HORIGUCHI FUMIO
KUROSAWA AKIRA
KUROSAWA AKIRA
Application Number:
JP2702882A
Publication Date:
August 26, 1983
Filing Date:
February 22, 1982
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/76; H01L21/302; H01L21/3065; H01L21/762; (IPC1-7): H01L21/302
Attorney, Agent or Firm:
Takehiko Suzue