PURPOSE: To reduce the number of processes, in the surface of an epitaxial n- type layer in an IIL co-located linear IC process, by performing p type isolation diffusion for electrically isolating elements and n type well diffusion of an IIL part by the same heat treatment process.

CONSTITUTION: Sb is deposited on a part of the surface of a p- type Si substrate 1. Si, in which low concentration P is doped, is epitaxially grown, and an n- type Si layer 2 is formed. An n+ type embedded layer 3 is embedded between the substrate 1 and the Si layer 2. An oxide film 4 is grown on the surface of the Si layer 2 Hot etching is performed and an isolation part 5 of B is deposited. A window is provided in the part 5. Thereafter glass is removed. After hot etching of a well part, the isolation part is covered by a mask 6, and P impurity ions are implanted. Then, the B in the isolation part is elongated by heat treatment and diffused. A p type layer 7 reaching the substrate 1 is formed. P in the well part is elongated and diffused, and n type well part 8 reaching n+ type embedded layer is formed. Thus a linear region I and an IIL region II are obtained.