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Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS62165369
Kind Code:
A
Abstract:

PURPOSE: To facilitate manufacture of a semiconductor device such as an EP- ROM cell with simple processes and with a high reliability by a method wherein a part of 1st gate electrode material is selectively etched and isolated and the exposed surface of a substrate is doped with 2nd conductivity type impurity to form 2nd conductivity type diffused layers.

CONSTITUTION: After resist is applied to 1st polycrystalline silicon film 34, a part of the 1st polycrystalline silicon film 34 is selectively etched and isolated with the resist as a mask. Then, after the resist is removed, the gate oxide film 33 which is exposed in a source forming region is removed by etching. Then a heat treatment is carried out and n+ type diffused layers 35 are formed in the surfaces of a substrate 31 exposed in the source forming region. Successively, a PSG film formed on the 1st polycrystalline film 34 surface is removed. Then, diluted oxidation is carried out and a polycrystalline silicon oxide film 36 with the thickness of 300 is formed on the 1st polycrystalline silicon film 34 surface. At that time, hot oxide films 36' are formed on the n+ type diffused layer 35 surfaces. 2nd polycrystalline silicon film 37 is deposited over the whole surface and then doped with phosphorus.


Inventors:
SHINADA KAZUYOSHI
Application Number:
JP1986000006910
Publication Date:
July 21, 1987
Filing Date:
January 16, 1986
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/8247; H01L29/78; H01L29/788; H01L29/792; (IPC1-7): H01L29/78



 
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