PURPOSE: To obtain the manufacturing method suitable for microscopical formation and a high speed operation of the title semiconductor device by a method wherein the emitter region of a bipolar transistor is surrounded by polycrystalline silicon formed simultaneously with the gate polycrystalline silicon of a field-effect transistor, it is used as a mask and the estimation of the anticipation of mask-matching deviation is unnecessitated.

CONSTITUTION: When a semiconductor device is manufactured by forming a silicon gate MOS field-effect transistor and a bipolar transistor, the emitter region 15 of the bipolar transistor is surrounded by a polycrystalline silicon which will be formed simultaneously with the gate polvcrvstalline silicon 9 of a field-effect transistor, and it is used as a mask. For example, when the gate polycrystalline silicon layer 9 of a CMOS transistor is formed, a polycrystalline silicon layer to be used as an ion-implantation mask is formed on the emitter forming part of the bipolar transistor. Then, the source and drain region 11 of an NMOS transistor and the emitter region 15 of the bipolar transistor are formed by the self-aligement of the polycrystalline silicon layer.