Title:
MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH0992597
Kind Code:
A
Abstract:
To prevent an upper resist layer and a lower resist layer from being mixed together at an interface between them when a resist pattern is formed through a multilayer resist method.
A first resist film 4 is deposited on a semiconductor substrate 1, pre-baked at a temperature of 100°C or so, and then baked at a high temperature (150°C or so) for a short time to make its surface hardened, and then a second photoresist film is deposited on the first photoresist film 4.
Inventors:
FUKUMOTO YOSHIKO
Application Number:
JP24586395A
Publication Date:
April 04, 1997
Filing Date:
September 25, 1995
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G03F7/38; H01L21/027; (IPC1-7): H01L21/027; G03F7/38
Attorney, Agent or Firm:
Yamato Tsutsui