Title:
MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS61110426
Kind Code:
A
Abstract:
PURPOSE:To form a contact hole without over etching and unetched region to an insulating film having difference in thickness by previously removing an insulating film of thick region, thereafter forming a thin insulation film and simultaneously etching the region of reduced thickness and the thin insulating film. CONSTITUTION:An N<-> epitaxial layer 11 is formed on a P<+>Si substrate land SiO24 is formed while N<+> layer is formed within a diffusion window of SiO23. The SiO24 on the N<+> layer is totally removed and photo processing is carried out, and etching is then carried out using the SiO2 etchant for SiO23 to form the holes 21, 22. This etching removes SiO2 at the area where etching may easily be left due to thick SiO2 at the area where becomes a contact hole later and thereby the holes 21, 22 are formed. Next, the SiO212 which will become a capacitor is accurately controlled for thickness by the Si oxidation technique. The photo processing is carried out again, etching is carried out for SiO212 and thereby the contact holes 5-9 can be completed.
Inventors:
MORIKAWA HISASHI
Application Number:
JP23257884A
Publication Date:
May 28, 1986
Filing Date:
November 05, 1984
Export Citation:
Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
H01L21/28; H01L21/302; H01L21/3065; (IPC1-7): H01L21/306
Attorney, Agent or Firm:
Kugoro Tamamushi