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Title:
MANUFACTURE OF SEMICONDUCTOR MEMORY UNIT
Document Type and Number:
Japanese Patent JPS57162459
Kind Code:
A
Abstract:

PURPOSE: To prevent invasion of electrons from the outside and to catch surely electrons held in a memory cell of semiconductor memory unit by a method wherein a semiconductor substrate is baked to form many number of cores for defect in the substrate, the back of the substrate is roughened, baking is performed again to make the no defect region to be generated on the surface part, and the deired memory circuit is provided thereon.

CONSTITUTION: An Si single crystal containing proper quantities of C and O to form the cores for generation of crystal defect is formed by the pulling method, and the surface of the substrate 1 obtained by slicing it is ground. Then baking is performed at 800°C in the N2 atmosphere for about 2hr to form the cores for defect collecting O to C in the inside of the substrate 1, and lapping is performed on the back to roughen the back face forming mechanical damage. After then, the surface thereof is covered with an SiO2 film 2, and Si3N4 films 3 are provided at the prescribed regions, patterning is performed on the film 2 by the photoetching method, and heat treatment is performed to form thick field oxide film 4 at the exposed parts of the substrate 1, while the thin no defect regions are made to be generated at the element forming regions of the substrate 1. Then thin insulating films 5 surrounded with the films 4 are provided as usual, and the diffusion region, etc., are formed in succession.


Inventors:
IIZUKA YASUO
NARITA TAKAMICHI
Application Number:
JP4803381A
Publication Date:
October 06, 1982
Filing Date:
March 31, 1981
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L27/10; H01L27/108; H01L29/78; (IPC1-7): G11C11/34; H01L27/10; H01L29/78



 
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