PURPOSE: To prevent the concentration of an electric field in the vicinity of the upper end of an element isolation region by burying an insulator layer and a polycrystalline silicon layer into an opening formed as element isolation, coating sections except the opening with a silicon nitride layer for preventing oxidation and forming a selective oxide film at the upper end section of the opening through oxidation treatment.

CONSTITUTION: An opening 56 is formed into a semiconductor substrate 50, and the opening 56 is coated with a non-doped insulator layer 57 while a P-type inversion- preventive impurity region 58 is shaped. A third silicon oxide layer 59 is buried into the opening 56, and the surface of the layer 59 is smoothed through etchback while the level of the surface of the layer 59 is made lower than the surface of the P-silicon semiconductor substrate 50. A second polycrystalline silicon layer 60 is buried sufficiently into the opening 56, and a first polycrystalline silicon layer 53 on a silicon nitride layer 52 and the second polycystalline silicon layer 60 are also oxidized sufficiently. Consequently, a selective oxide layer 62 is formed onto the third silicon oxide layer 59 while an element isolation region having bird beaks 61 at the ends of the element isolation region is shaped. Accordingly, the width of the element isolation region can be reduced largely.