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Title:
MANUFACTURE OF SOI SUBSTRATE
Document Type and Number:
Japanese Patent JPH04206949
Kind Code:
A
Abstract:

PURPOSE: To easily form a diffused layer into a buried layer formed already and positively form NPN or PNP transistor without increasing the processing time and man-hours by isolating elements after forming a P-type bufied layer on a P-type well formed previously.

CONSTITUTION: For isolation, a polycrystalline silicon 8 is deposited deeper than buried layers 4, 6. A level-different part 12 is generated by the heat treatment at the surface of wafer. Before attaching a second silicon wafer 11, spin- on-glass 13 for burying the level-different part 12 is spin-coated to make flat the surface 14. The pin-on-glass 13 is sandwiched for attaching on a second wafer 11. Next, a composite wafer is placed upside down so that the wafer 1 is placed as the upper layer and the upper layer is ground and wrapped until the layer of polycrystalline silicon 8 appears and the prescribed thickness can be obtained. Islands 19 of PNP transistors having the P type buried layers can be formed without executing the diffusion process which requires accuracy such as formation of the P type buried layer into the N type buried layer.


Inventors:
NODA SHUJI
Application Number:
JP33929090A
Publication Date:
July 28, 1992
Filing Date:
November 30, 1990
Export Citation:
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Assignee:
AISIN SEIKI
International Classes:
H01L27/12; H01L21/02; H01L21/74; H01L21/76; H01L21/762; H01L21/8228; H01L27/082; (IPC1-7): H01L21/74; H01L21/76; H01L27/082; H01L27/12
Attorney, Agent or Firm:
Hiroshi Okawa



 
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