PURPOSE: To constitute an SIT and an MOSFET to the same semiconductor substrate, and to improve characteristics by forming all of a source region and a gate region in the SIT and a gate region in the MOSFET in self-alignment structure.

CONSTITUTION: A gate oxide film 65 is formed in an n channel MOS transistor (Tr) forming prearranged region 62, a p channel MOSTr forming prearranged region 63 and an MOSTr gate capacitance forming prearranged region 64, and non-doped poly Si 66 as a first layer functioning as a gate electrode is deposited. Si 66 is etched while using a photo-resist 44 as a mask to shape n channel and p channel MOSTr gate electrode 67 and SIT gate electrode 68. An Si3N4 film 56 in an SIT source prearranged region 54 and SiO2 43 are removed while employing the resist 44 as a mask. Consequently, the region 54 can be positioned accurately. Second layer non-doped poly Si 103 is deposited, and Si 103 except the region 54 is removed. P+ ions are implanted 48 to Si 103, and an SIT source region 104 is formed through heat treatment.