Title:
MANUFACTURE OF VERTICAL MOS TRANSISTOR
Document Type and Number:
Japanese Patent JP3198200
Kind Code:
B2
Abstract:
PURPOSE: To improve the stability of a breakdown voltage characteristic obtained between the drain and source of a vertical MOS transistor, by increasing the conductivity of its first gate electrode through doping an impurity therein, and also, by giving an enough conductivity to the bottom part of its first gate electrode while repeating plural times the doping of the impurity from the surface of its substrate after depositing undoped polysilicon on the surface of its substrate.
CONSTITUTION: On the surface of an N+-type single crystal semiconductor base substance 1, an N- epitaxial layer 2, a second impurity region 3 and a first impurity region 4 are formed in succession. On the surface of a substrate formed in this way, undoped polysilicon is deposited, and an impurity is diffused therein. In a groove formed therein, a doped polysilicon layer 6 is buried, and after the layer 6 is patterned a second gate electrode 6 is formed. In a second insulation film part contacted with the doped polysilicon layer 6, a second gate insulation film 7 and an insulation film 8 for a capacitor are formed respectively. Subsequently, an interlayer insulation film 13 is deposited on the surface of the substrate, and contact holes are bored in the layer 13, and further, in the N+ source region 4 and the P+ base region 3, a source electrode 11 and a gate electrode 6a are formed respectively. Then, on the rear surface of the semiconductor substrate, a drain electrode 12 is formed out of a metallic film.
More Like This:
| JP3551183 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE |
| JPH06275524 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR |
| JPH07326743 | PLANAR TYPE SEMICONDUCTOR DEVICE |
Inventors:
Noboru Matsuda
Yoshiro Baba
Satoshi Yanagiya
Yoshiro Baba
Satoshi Yanagiya
Application Number:
JP12802693A
Publication Date:
August 13, 2001
Filing Date:
April 30, 1993
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L29/78; H01L21/336; H01L29/40; (IPC1-7): H01L29/78
Domestic Patent References:
| JP4229662A |
Attorney, Agent or Firm:
Eiji Morota