Title:
TFT基板の製造方法
Document Type and Number:
Japanese Patent JP4654581
Kind Code:
B2
Abstract:
To provide a manufacturing method which prevents the corrosion of a metal wiring during an ITO (indium tin oxide) wet etching process and conducts in-plane uniform patterning of ITO.
A TFT (thin film transistor) substrate, having a plurality of TFT elements, disposed on a display area and a conductive part 112 connected to the specified TFT element and having a connection terminal for the external connection, in a non-display area, is provided with a silicon nitride film 380 disposed on the overall surface of the display area and the non-display area and a silicon oxide film 600 disposed on the silicon nitride film.
COPYRIGHT: (C)2005,JPO&NCIPI
Inventors:
Junichi Taira
Application Number:
JP2004023925A
Publication Date:
March 23, 2011
Filing Date:
January 30, 2004
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G09F9/30; G09F9/00; H01L51/50; H01L21/28; H01L21/336; H01L27/32; H01L29/417; H01L29/423; H01L29/49; H01L29/786; H05B33/14
Domestic Patent References:
| JP2002318555A | ||||
| JP2003031817A | ||||
| JP11097691A | ||||
| JP2003338509A | ||||
| JP2001318626A | ||||
| JP2001350158A | ||||
| JP2002352950A | ||||
| JP7326768A | ||||
| JP2002134527A | ||||
| JP2003068757A |
Attorney, Agent or Firm:
Kazuya Nishi
Masatake Shiga
Kazunori Onami
Masahiko Ueyanagi
Osamu Suzawa
Masatake Shiga
Kazunori Onami
Masahiko Ueyanagi
Osamu Suzawa