Title:
貼り合わせ半導体ウェーハの製造方法
Document Type and Number:
Japanese Patent JP4750065
Kind Code:
B2
Inventors:
Hiroaki Yamamoto
Hirotaka Kato
Hiroshi Furukawa
Kazuaki Fujimoto
Hirotaka Kato
Hiroshi Furukawa
Kazuaki Fujimoto
Application Number:
JP2007087340A
Publication Date:
August 17, 2011
Filing Date:
March 29, 2007
Export Citation:
Assignee:
sumco tech xiv Co., Ltd.
International Classes:
H01L21/02; H01L21/762; H01L27/12
Domestic Patent References:
| JP398581B2 | ||||
| JP8250688A | ||||
| JP8055768A | ||||
| JP7029782A | ||||
| JP5055100A | ||||
| JP62205617A | ||||
| JP64071115A | ||||
| JP4286310A | ||||
| JP4162630A | ||||
| JP3097215A | ||||
| JP2056916A | ||||
| JP62264651A |
Attorney, Agent or Firm:
Hideharu Tanaka