Title:
強誘電体メモリ装置の製造方法
Document Type and Number:
Japanese Patent JP5241489
Kind Code:
B2
Abstract:
A ferroelectric memory device and a manufacturing method thereof are provided to simplify manufacturing processes and to reduce fabrication costs by using a channel forming layer made of an organic semiconductor layer. A ferroelectric memory device comprises a substrate(10), a gate electrode, drain/source electrodes, a ferroelectric layer, and a channel forming layer. The gate electrode(21) is formed on the substrate. The drain/source electrodes(24,25) are formed both sides of the gate electrode on the substrate. The ferroelectric layer(23) is formed on the gate electrode. The ferroelectric layer is made of a PVDF layer. The channel forming layer(22) is interposed between the gate electrode and the ferroelectric layer. The channel forming layer is made of an organic semiconductor layer.
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Inventors:
Park, Byung-un
Application Number:
JP2008511056A
Publication Date:
July 17, 2013
Filing Date:
May 11, 2006
Export Citation:
Assignee:
University of Seoul Foundation of Industry-Academic Co-op
International Classes:
H01L21/8246; H01L27/105; H01L27/28; H01L51/05; H01L51/30
Domestic Patent References:
| JP5114732A | ||||
| JP2004040094A | ||||
| JP2004282050A | ||||
| JP2003343578A |
Foreign References:
| WO2004003972A1 |
Attorney, Agent or Firm:
Kyosei International Patent Office