MANUFACTURING METHOD OF INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT MANUFACTURED BY SAID METHOD

Japanese Patent JPH06177090

A

PURPOSE: To conduct etching of an etching layer to a decided depth by using a reference layer and a stop layer as an auxiliary mask, and simultaneously conducting the etching of the etching layer and the reference layer by a wet-type or dry-type chemical attack, until it reaches the stop layer. CONSTITUTION: A stop layer 2 is deposited on an etching layer 1, and a reference layer 3, formed of materials compatible with the etching layer 1, is deposited on the stop layer 2. Next, one part of the reference layer 3 is covered with an etching mask 4, and the etching of the exposed part of the reference layer 3 is operated by the wet-type or dry-type chemical attack, until it reaches the stop layer 2. Then, the etching mask 4 and the exposed part of the stop layer are excluded, and then the reference layer 3 and the stop layer 2 are used as the auxiliary mask, and the etching of the exposed part of the etching layer 1 and the reference layer 3 is conducted concurrently by the chemical attack, until the etching reaches the stop layer 2. Thus, an etching having a depth substantially proportional to the thickness (e) of the reference layer 3 can be formed in the etching layer 1.

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MITSUSHIERU AON

JP32703891A

June 24, 1994

November 15, 1991

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CENTRE NAT ETD TELECOMM

H01L21/033; H01L21/302; H01L21/28; H01L21/3065; H01L21/308; (IPC1-7): H01L21/302

Masatake Shiga (3 outside)

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