To provide a manufacturing method for a laminated electronic component which has a small cutting clearance and a high dimensional accuracy, and in which there is no defect generation after baking by stress and strain.

A laminated green sheet 21 contains a plurality of dielectric layers 32 and a plurality of electrode layers 33. A cutting process 2 contains a process in which the green sheet 21 is irradiated with laser beams 92 and the green sheet 21 is cut into laminated green chips 31. The laminated green chip 31 is cut out so as to be formed in a square shape comprising sides in which the length of one side is ≤0.6 mm, and sides in which the length of one side is ≤0.3 mm by sizes after the baking.