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Title:
MANUFACTURING METHOD OF, MEASURING DEVICE FOR, AND WAFER FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2007035856
Kind Code:
A
Abstract:

To provide a manufacturing method of, a measuring device for, and a wafer for an integrated circuit, capable of carrying out a more accurate probe test while reducing the damage to a bonding pad.

A sensor cell 21 is provided between chip forming regions on the wafer 10. A diaphragm 25 is formed on this sensor cell 21, and sensor pads 31-34 connected to a doped region 27 are provided on the surface of the diaphragm 25. Probe needles 50 are brought into contact with the sensor pads 31-34, and the voltage in relation to the strain of the doped region 27 at that point is measured via the probe needles 50 in contact with the sensor pads 33, 34. The relative tilt angle and the relative distance are determined based on this measured voltage between the probe card on which the probe needles 50 are installed and the wafer 10, and the probe needles 50 are connected to the bonding pads of the wafer 10 to carry out a current feeding test so that the relative position is maintained in accordance with them.


Inventors:
KOMATSU KENJI
NAKAJO AKIRA
Application Number:
JP2005215993A
Publication Date:
February 08, 2007
Filing Date:
July 26, 2005
Export Citation:
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Assignee:
FREESCALE SEMICONDUCTOR INC
International Classes:
H01L21/66; G01R31/28
Domestic Patent References:
JPH09246332A1997-09-19
JPH0414847A1992-01-20
JPH08306751A1996-11-22
Attorney, Agent or Firm:
Mamoru Kuwagaki