Title:
パッケージチップの製造方法
Document Type and Number:
Japanese Patent JP7391465
Kind Code:
B2
Abstract:
To provide a manufacturing method for a package chip capable of suppressing quantity of a burr which is residual between package chips.SOLUTION: A manufacturing method for a package chip includes: a half cut step of cutting a package substrate from one side of the package substrate to a predetermined depth along each predetermined dividing line using an annular cutting blade, thereby forming a half cut groove having a depth which does not reach the other side which is positioned at an opposite side of the one side of the package substrate in a thickness direction of the package substrate and having a V-shaped or curved cross section which is orthogonal to a length direction of each predetermined dividing line, in each of multiple electrodes which are disposed along the predetermined dividing lines; a processing step of applying plating processing to the multiple electrodes after the half cut step; and a full cut step of cutting the half cut groove after the plating processing step, cutting the multiple electrodes in the thickness direction and cutting the package substrate, thereby forming a package chip.SELECTED DRAWING: Figure 5
Inventors:
Daigo Hozumi
Chikako Imoto
Chikako Imoto
Application Number:
JP2019059004A
Publication Date:
December 05, 2023
Filing Date:
March 26, 2019
Export Citation:
Assignee:
Disco Co., Ltd.
International Classes:
H01L21/301
Domestic Patent References:
| JP2005038927A | ||||
| JP2018152390A | ||||
| JP7169796A | ||||
| JP2017038051A | ||||
| JP2007258590A | ||||
| JP2014090126A | ||||
| JP7335591A | ||||
| JP2015142088A | ||||
| JP2015109349A |
Attorney, Agent or Firm:
Akira Matsumoto
Tomohiro Okamoto
Takahiro Kasahara
Hideaki Okamoto
Takayuki Okano
Tomohiro Okamoto
Takahiro Kasahara
Hideaki Okamoto
Takayuki Okano