To reduce property variations in a TFT using a CG silicon film.

The method comprises a process (a) for preparing a substrate having an insulating surface, a process (b) for forming an amorphous silicon film on the insulating surface, a process (c) for carrying out a plasma treatment selectively to the amorphous silicon film of a second region 57 having prescribed positional relationship to a first region 56 wherein each channel region of a plurality of semiconductor elements is formed, a process (d) for introducing catalyst element for accelerating crystallization almost all over the amorphous silicon film after the process (c), a process (e) for forming a CG silicon film by crystallizing the amorphous silicon film after the process (d) and a process (f) for forming a channel region of a plurality of semiconductor elements by using the crystalline silicon film of the first region 56.