Title:
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND INSPECTING METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2012028758
Kind Code:
A
Abstract:
To provide an inspection method that accurately detects a low reliable transistor with low stress in a shorter time than a bias-temperature (BT) test, and to efficiently manufacture a highly reliable electronic apparatus by determining a highly reliable transistor in a shorter time than the BT test.
The reliability of a transistor can be determined by performing Vg-Id measurement while the transistor is irradiated with light, because the hysteresis characteristic obtained as a result of the measurement is correlated with the result of a BT test. This can provide an inspection method that accurately detects a low reliable transistor with low stress in a shorter time than the BT test.
Inventors:
GOTO HIROMITSU
YOSHITOMI SHUHEI
YOSHITOMI SHUHEI
Application Number:
JP2011137590A
Publication Date:
February 09, 2012
Filing Date:
June 21, 2011
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB CO LTD
International Classes:
H01L21/66; H01L29/786
Domestic Patent References:
JPH06291353A | 1994-10-18 | |||
JP2009277701A | 2009-11-26 | |||
JP2006165528A | 2006-06-22 |