Title:
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3424405
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce a quantity of masks for ion implantation at the step of forming a channel stopper on a twin well surface.
SOLUTION: A first ion implantation mask 2 which decides a channel stopper forming region on a substrate 1 is formed and B is implanted into all over the substrate surface by a high accelerating voltage. After that a second ion infusing mask 3 having a opening 3a which decides a second conductive well 5 forming region is formed. P is implanted into all over the opening 3a by a high accelerating voltage and As is implanted into a channel forming region of the second conductive well 5 by a low accelerating voltage by using the first and the second ion implantation masks. After that a well is formed by B and P being forcedly diffused perfused. After that p-channel stopper 7 is formed by B being implanted by a low accelerating voltage by using the first ion implantation mask 2.
Inventors:
Akiyoshi Watanabe
Application Number:
JP24169295A
Publication Date:
July 07, 2003
Filing Date:
September 20, 1995
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L21/761; H01L21/8238; H01L27/08; H01L27/092; (IPC1-7): H01L27/08; H01L21/761; H01L21/8238; H01L27/092
Domestic Patent References:
| JP5817655A | ||||
| JP1209756A | ||||
| JP61120460A | ||||
| JP5817657A |
Attorney, Agent or Firm:
Junichi Yokoyama
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